Hi,
I'm using an LX4F230H5QR FIGA3 running at 50 MHz. Here is my clock init:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
The device is configured as an SPI master and it is my understanding that bit rates are achievable up to SysClk/2, which in my case is 25 MHz.
I'm trying to configure the bit rate to be as close to 16 MHz as possible. When I use this line to configure the SSI Clock:
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, 1000000, 16);
I always measure a few MHz faster bit rate on my oscilloscope than configured. And anything higher than about 12.8 MHz will just set the bit rate to 25 MHz.
I also tried direct register control to manually configure the ssi clock without the library using these lines:
HWREG(SSI0_BASE + SSI_O_CPSR) = 3;
temp = HWREG(SSI0_BASE + SSI_O_CR0);
HWREG(SSI0_BASE + SSI_O_CR0) = (temp & 0xFFFF00FF);
Setting CPSR to 3 and SCR to 0 should give me an ssi bit rate of about 16,666,666 Hz, but the bit rate actually ends up being 25 MHz.
Configuring the ssi clock to be low (around 1 or 2 MHz) will yield the proper rate, but as 13 MHz is approached, the error gets higher until the ssi module just uses 25 MHz.
I have verified that my system clock is running at 50 MHz as well.
I checked the errata for the part and found nothing relevant. Am I doing something obviously wrong here or is it just not possible?