Changing ADC sample rate in RCGC0 results in ADC clock disabled

Hi everyone,

So I found a weird behavior. All this in ADC0, didn't fully tested ADC1

When I change the ADC max sample rate in RCGC0 for some reason the ADC clock gets disabled and I don't know why. I know they are legacy registers but is this normal?

Also, why is there no Tivaware function to set up the ADC max sample rate? Not in the legacy registers, nor on the ADC registers. Is the only way through HWREG / direct register method?