TMS320C6727: DMAX read through McASP random behavior

Part Number:TMS320C6727

Hi, 

I'm sending from an FPGA thirteen 32 bits words every 25us on the mcasp_rx[0] pin of my DSP running at 50Mhz. There are 32 spare clock cycles after every word.

The McASP is configured as follow : (burst mode, 32bits, NO_DMAX defined...)

void McASP0_start( void )
{
	unsigned	i,gblctl_temp;
	
	GBLCTL_0=		0x00000000;
	while(GBLCTL_0!=0x00000000);

	PWRDEMU_0=		0x00000001;

	RMASK_0=		0xFFFFFFFF;	
#ifdef NO_DMAX
	RFMT_0=			0x000000F8;
#else
	RFMT_0=			0x000000F0;
#endif		
	AFSRCTL_0=		0x00000000;		
	ACLKRCTL_0=		0x00000000;		
	AHCLKRCTL_0=	0x00000000;		
	RTDM_0=			0x00000001;		
	RINTCTL_0=		0x00000000;
	
	XMASK_0=		0xFFFFFFFF;		
	XFMT_0=			0x000000F8;		
	AFSXCTL_0=		0x00000002;		
	ACLKXCTL_0=		0x000000C0;		
	AHCLKXCTL_0=	0x00000000;		
	XTDM_0=			0x00000001;		
	XINTCTL_0=		0x00000000;
	
	for(i=0;i<NB_SERIALIZER_MCASP0;i++)
	{
		SRCTL_0(i)=	0x00000000;		
	}
		
	SRCTL_0(0)=		0x00000002;
	SRCTL_0(1)=		0x00000001;
	
	PFUNC_0=		0x4A00FFF0;		
	PDIR_0=			0x1000000A;		
	DITCTL_0=		0x00000000;
	DLBCTL_0=		0x00000000;	
	AMUTE_0=		0x00000000;

	GBLCTL_0=		0x00000202;
	while(GBLCTL_0!=0x00000202);

#ifndef NO_DMAX
		DMAX_mcasp0_start_fifo();
#endif

	XSTAT_0=		0x0000FFFF;
	RSTAT_0=		0x0000FFFF;
 
	gblctl_temp=GBLCTL_0|GLBCTL_RSRCLR|GLBCTL_XSRCLR;
	GBLCTL_0=gblctl_temp;
	while(GBLCTL_0!=gblctl_temp);

	gblctl_temp=GBLCTL_0|GLBCTL_RSMRST|GLBCTL_XSMRST;
	GBLCTL_0=gblctl_temp;	
	while(GBLCTL_0!=gblctl_temp);

	gblctl_temp=GBLCTL_0|GLBCTL_RFRST|GLBCTL_XFRST;
	GBLCTL_0=gblctl_temp;
	while(GBLCTL_0!=gblctl_temp);
}

If I read the received values from RBUF_0, every thing is fine, all data are received as expected. The McASP is then well configured for my application !!!

I now use the DMAX to read automatically the datas in a fifo.

The DMAX is configured as follow  (NO_DMAX is undefined now):

#define DMAX_FIFO_SIZE 130
#define DMAX_FRAME_SIZE 13

unsigned	Dmax_fifo_descriptor_mcasp0[7],
		Dmax_fifo_buffer_mcasp0[DMAX_FIFO_SIZE];

void DMAX_mcasp0_start_fifo (void)
{
	unsigned			i;

	Dmax_mcasp0_number_of_restart_counter++;
	for(i=0;i<DMAX_FIFO_SIZE;i++)
	{
		Dmax_fifo_buffer_mcasp0[i]=0xDEADBEEF; 
	}
	DEDR=			0x00000020;
	
	LOMAX_EVENT_05_ENTRY_MCASP0_RX=	0x01112804;
	
	LOMAX_TRANSFER_00_ENTRY_00=		MCASP0_DMA_PORT_ADDR;			
	LOMAX_TRANSFER_00_ENTRY_01=		((unsigned)Dmax_fifo_descriptor_mcasp0);		
	LOMAX_TRANSFER_00_ENTRY_02=		0x00000001;
	LOMAX_TRANSFER_00_ENTRY_03=		0x00000001;										
	LOMAX_TRANSFER_00_ENTRY_04=		0x00000000;								
	LOMAX_TRANSFER_00_ENTRY_05=		0x00000001;			
	LOMAX_TRANSFER_00_ENTRY_06=		MCASP0_DMA_PORT_ADDR;											
	LOMAX_TRANSFER_00_ENTRY_07=		MCASP0_DMA_PORT_ADDR;			
	LOMAX_TRANSFER_00_ENTRY_08=		0x00000000;												
	LOMAX_TRANSFER_00_ENTRY_09=		0x00000000;
	LOMAX_TRANSFER_00_ENTRY_10=		0x00000000;
	
	Dmax_fifo_descriptor_mcasp0[0]=		((unsigned)Dmax_fifo_buffer_mcasp0);
	Dmax_fifo_descriptor_mcasp0[1]=		0x00000000;
	Dmax_fifo_descriptor_mcasp0[2]=		(0x2<<24) + DMAX_FIFO_SIZE;
	Dmax_fifo_descriptor_mcasp0[3]=		0x00000000;
	Dmax_fifo_descriptor_mcasp0[4]=		DMAX_FRAME_SIZE-1;
	Dmax_fifo_descriptor_mcasp0[5]=		0x01000000;
	Dmax_fifo_descriptor_mcasp0[6]=		0x00000000;
	
	DELPR=			0x00000020;
	DEPR			|= 0x00000020;
	DFSR0=			0x00000003;
	DTCR0=			0x00000002;
	DEFR=			0x00000020;
	DEER=			0x00000020;
}

As I understand, DMAX is configured to send an interrupt every thirteen 32 bits received words on the McASP. Datas are written automatically in fifo.

In the interrupt 7 function, I read the 13 last received data from the fifo, but once in a while data[9] or data[10] is 1 bit right rotated.

I don't understand why. Can someone have an explanation for this behavior and a workaround ?

thanks