Part Number:MSP430F5510
Tool/software: Code Composer Studio
Hi, Friends.
I have issue with my device.
The device is built on the msp430f5510 and is powered by a 3.6 V battery.
To the 5510 via SPI (USCI_B-based) are connected the flash memoryAT25256B-SSHL-T and the cc1120 radio module. Also through USCI_A there is a periodic poll on UART protocol Modbus.
To the MCU an external quartz (32768 Hz) is connected, from which ACLK and RTC_A are powered.
I decided to use MCLK = 8 MHz, SMCLK = 4 MHz, ACLK = XT1 = 32768 Hz.
This should improve the processing speed of information and allow the chip to go faster to LPM3. Since according to the datasheet the typical consumption at a frequency of 1 MHz is 0.25 mA, at a frequency of 8 MHz = 1.55 mA, which gives a difference of 6.2 in favor of 1 MHz. But the processing speed at 8 MHz is 8 times higher, which will allow the chip to process the commands in a shorter period of time and fall asleep.
Flash memory with a voltage of 1.8 V can operate at a frequency of 5 MHz. Therefore, I want to lower the SMCLK frequency to 4 MHz, which will allow to keep the flash and radio module operability when the battery voltage drops, also at a high level.
Based on the above, I get the following situation.
1) I can not correctly calculate the register values for the 8MHz frequency.
P5SEL |= BIT4+BIT5; //Enable XIN XOUT on P5.4 и P5.5
UCSCTL6 |= XT2OFF; //Desabling XT2
UCSCTL6 &= ~(XT1OFF); //Enable XT1
UCSCTL6 |= XCAP_3; //Use internal cap
UCSCTL3 = SELREF_2; // DCO FLL reference = REFO
UCSCTL4 = SELA_0; //ACLK = XT1
UCSCTL0 = 0x0000; //
//Wait for ocs stabilization
do{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
} while (UCSCTL7 & XT1LFOFFG);
__bis_SR_register(SCG0); //Disabling FLL control
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz
UCSCTL2 |= 249; // Set DCO multifier for 8MHz
// (N + 1) * FLLRef = Fdco
// (122+1) * 32768 = 4030464
// (249 + 1) * 32768 = 8192000 is not 8MHz and up for power is 1,8V !!!
__bic_SR_register(SCG0); // Enable control FLL
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);
/* ******** Init USCI_B UART Mode ******* */
UCA1CTLW0 |= UCSWRST; //Reset UART
UCA1CTLW0 |= UCSSEL__SMCLK; //CLK = SMCLK
// Calculate port speed
// 8000000/(16*9600) = 52
// Use table 34-6 in Family User Guide
UCA1BR0 = 52; //8000000/16/115200
UCA1BR1 = 0x00;
UCA1MCTL |= UCBRS_6 + UCBRF_0 + UCOS16; //Set modulation,
UCA1CTL1 &= ~UCSWRST; //Starting UART
UCA1IE|=UCRXIE; //Wait incomming request
UCB1CTL1 |= UCSWRST; // reset SPI
UCB1CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC; //Clock Phase + First MSB + SPI master + Synhro mode
UCB1CTL1 |= UCSSEL_2; // CLOCK = SMCLK
UCB1BR0 = 0x52; // By table 39-5
UCB1BR1 = 0; //
//UCB1MCTL = 0; // Clear SPI
UCB1CTL1 &= ~UCSWRST; // USCI Start
UCB1IE |= UCRXIE;
But according to my calculations, the MCU frequency is not 8,000,000, but 8,192,000.And so the dividers obtained are not applied correctly.
And at 1.8V power the DCO frequency can not be 8192000. And I also do not understand how to correctly set the SMCLK frequency to 4 MHz, for spi.
2) And then there is the question of the correct setting of SPI, if there is a conflict with the flash memory and the cc1120 chip during my conflict settings. Whether they have the same SPI port modes, or cc1120 will accept what msp430f5510 indicates and I can specify the settings for the flash.
I'm sorry, but I'm new to programming chips. and there are difficulties with English, so I use a google translator. But I need to modify the firmware of the device within a week. Therefore, for correct operation, I want to properly configure all the modules, and then finish the functionality.
Thank you in advance for your cooperation.