Hello,
I'm trying to created an operable AIS image using the following .ini file. for the OMPA-L138 ZCE E
1. The device needs to boot in secure mode from SPI0.
2. One of the first commands which needs to be executed are turning the Rx led on. even this doesn't happens.
could someone have a look on in my .ini file and answer the following questions:
a. Are all my IO/Taps etc configuration are configured correctly?
b. Do I need to configure any PLLs, Timers etc, currently all initialization are in the code itself.
c. What is the difference between generic to custom security type?
Thanks,
Roee.
This is my file:
[General]
BootMode=SPIMASTER
crcCheckType=NO_CRC
;__________________________________________________________
;BSR Add Start:
; Security settings (keys, options, list of sections to encrypt, etc.)
[Security]
securityType = GENERIC
bootExitType = SECUREWITHSK
genericJTAGForceOff = TRUE
encryptSections = ALL
; CEK used for AES encryption of data - must be string of 32 hexadecimal characters
encryptionKey = **my key**
; SHA Algorithm Selection
genericSHASelection = SHA256
; Binary file containing secure key header for generic device
genKeyHeaderFileName = myheaderfile.bin
;BSR_Add End
;__________________________________________________________
; This section allows setting the PLL0 system clock with a
; specified multiplier and divider as shown. The clock source
; can also be chosen for internal or external.
; |------24|------16|-------8|-------0|
; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
;[PLL0CONFIG]
;PLL0CFG0 = 0x00180001
;PLL0CFG1 = 0x00000205
; This section allows setting up the PLL1. Usually this will
; take place as part of the EMIF3a DDR setup. The format of
; the input args is as follows:
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
; PLL1CFG1: | RSVD | PLLDIV3|
;[PLL1CONFIG]
;PLL1CFG0 = 0x00000000
;PLL1CFG1 = 0x00000000
; This section lets us configure the peripheral interface
; of the current booting peripheral (I2C, SPI, or UART).
; Use with caution. The format of the PERIPHCLKCFG field
; is as follows:
; SPI: |------24|------16|-------8|-------0|
; | RSVD |PRESCALE|
;
; I2C: |------24|------16|-------8|-------0|
; | RSVD |PRESCALE| CLKL | CLKH |
;
; UART: |------24|------16|-------8|-------0|
; | RSVD | OSR | DLH | DLL |
;[PERIPHCLKCFG]
;PERIPHCLKCFG = 0x00000000
;********************************************************************************
;******************************* 150 MHz DDR settings ***************************
;********************************************************************************
; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface.
; See PLL1CONFIG section for the format of the PLL1CFG fields.
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLL1CFG |
; PLL1CFG1: | PLL1CFG |
; DDRPHYC1R: | DDRPHYC1R |
; SDCR: | SDCR |
; SDTIMR: | SDTIMR |
; SDTIMR2: | SDTIMR2 |
; SDRCR: | SDRCR |
; CLK2XSRC: | CLK2XSRC |
;[EMIF3DDR]
;PLL1CFG0 = 0x18010001
;PLL1CFG1 = 0x00000002
;DDRPHYC1R = 0x000000C4
;SDCR = 0x0A034622
;SDTIMR = 0x1C912A08
;SDTIMR2 = 0x3811C700
;SDRCR = 0x00000494
;CLK2XSRC = 0x00000000
[MPUCONFIG]
MPUSELECT = 0x000001FF
STARTADDR = 0x00000000
ENDADDR = 0xFFFFFFFF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000000FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000100FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000200FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000300FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000600FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x00060707
MPPAVALUE = 0x00000000
[TAPSCONFIG]
TAPSCFG = 0xFFFFFFFF
;TAPSCFG = 0
;TAPSCFG = 0x0000FFFF
;TAPSCFG = 0xFFFFFFFF