Part Number:AM4372
Simply put, does the EMIF support DLL off operation with "low" clock speeds for DDR3 external memory? I can see there's a register bit to turn it OFF but it's nowhere elaborated if that would actually work in practical terms as EMIF reference does refer to DLL lock.
From SPRUHL7H
DLL off is referred in self refresh mode description:
9.3.3.4.1 Self-Refresh Mode
If the reg_ddr_disable_dll bit in the SDRAM Config register is 1, the EMIF issues a LOAD MODE
REGISTER command to the extended mode register 1 (pad_ba_o[2:0] = 0x1) with the pad_a_o bits set as follows:
Table 9-150 gives the relevant bit to set the SDRAM init to do this (MR1 A[0]) presumably automagically
Then there's this:
9.3.3.2 Clock Management
The EMIF can gate EMIF_FICLK. There is an internal mechanism that can stop EMIF_FICLK
automatically. EMIF_FICLK is stopped only after the SDRAM is put into self-refresh mode and the poweridle protocol on the local bus completes. The EMIF_FICLK frequency can be changed only after putting
the external SDRAM in self-refresh mode.
The EMIF waits for the DLL lock before performing any memory access.
Why do I wanna use DLL off anyways? Well, 300MHz min clock for DDR3 is still pretty high. It's just opening the door to more EMI woes. For this application e.g. 100MHz would be perfectly fine, especially as the cache would handle majority of the memory accesses anyways.