Part Number:TCI6638K2K
Hello, here’s some background:
I am developing with a Keystone II EVM (XTCIEVMK2X Rev 1.1: http://www2.advantech.com/Support/TI-EVM/EVMK2HX.aspx) as a stand in for a custom board using a 66AK2H12.
Previously, a team member of mine was able to demonstrate data transfer from an FPGA to the 66AK2H12 on our custom board using all four SRIO lanes and receiving the data on the SoC with a program that relied on the SRIO driver in Processor SDK Linux version 03.03.00 (Linux was running on the ARM cores).
Since support for the SRIO driver was dropped from later Processor SDK Linux releases (see PLSDK-1421) but remains in TI-RTOS which we were always planning on using on the DSPs I have been trying to work towards replacing the former with the latter.
I decided to start off small, with some of the example programs provided with Processor SDK RTOS (I am using ti-processor-sdk-rtos-k2hk-evm-04.03.00.05). Specifically I was trying to work with the SRIO tput_benchmarking test project (C:\ti\pdk_k2hk_4_0_9\packages\ti\drv\srio\test\tput_benchmarking) since it appears to offer a number of different modes to test where I could build up my understanding of the configuration required. I generated the project (alongside some of the other examples) without problem
C:\ti\pdk_k2hk_4_0_9\packages>pdksetupenv.bat "C:\ti\pdk_k2hk_4_0_9\packages"
C:\ti\pdk_k2hk_4_0_9\packages>pdkProjectCreate.bat K2K all little srio all dsp "C:\ti\pdk_k2hk_4_0_9\packages"
And successfully built it in CCS and ran it in the default mode (C-I-C) on cores 0 and 1.
According to the documentation in section 9.2 of SRIO_Benchmarking_Example_Code_Guide.doc (found under C:\ti\pdk_k2hk_4_0_9\packages\ti\drv\srio\test\tput_benchmarking\docs) it should be possible to simply change the USE_LOOPBACK_MODE definition in benchmarking.h from TRUE to FALSE in order to run the tests in C-E-C mode. The main difference I see is that instead of calling CSL_SRIO_SetLoopbackMode for each lane, CSL_SRIO_SetNormalMode is called instead.
I have the AMC SMA Ultra 9000 breakout board from Silicon Turnkey Express and all four lanes for SRIO (8-11) connected in loopback Tx+->Rx+ etc (section 5.2 of the guide document). When I build and try to run this mode (I also have DISPLAY_RUN_PROGRESS_MESSAGES set to true in benchmarking.h) this is what I see:
[C66xx_1] ********************************
*********** PRODUCER ***********
********************************
WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!
Debug(Core 1): Waiting for SRIO to be initialized.
[C66xx_0] ********************************
*********** CONSUMER ***********
********************************
WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!
Debug: Queue Manager and CPPI are initialized.
Debug: Waiting for module reset...
Debug: Waiting for module local reset...
SRIO Serdes Common Init Complete
SRIO Serdes Lane 0 Init Complete
SRIO Serdes Lane 1 Init Complete
SRIO Serdes Lane 2 Init Complete
SRIO Serdes Lane 3 Init Complete
SRIO Serdes Init Complete
Debug: Waiting for SRIO ports to be operational...
Debug: SRIO port 0 is NOT operational.
*Note: I cropped the subsequent output since the port isn’t operational and the tests don’t run
**Also Note that despite what the output messages say, core 0 (consumer) was started first, the messages only print after both cores are running…
Digging into where the “SRIO port 0 is NOT operational” message is not generated I can see that that it is due to CSL_SRIO_IsPortOk never returning a good port status (the function call stack is: main -> SrioDevice_init -> waitAllSrioPortsOperational -> CSL_SRIO_IsPortOk). By default, there is a timeout of 5 seconds but even eliminating that and waiting forever, no progress is made. Taking a peek at the Port General Control CSR using the register view in CCS, I can see that as expected bit 30 (Port OK) is indeed unset and that bit 31 (Port uninitialized) is set. My understanding is that either the port as wired/configured is never getting an idle control symbol or is not establishing proper input sampling window timing alignment (Sam Fuller, RapidIO The Embedded System Interconnect, pg 127-128).
I am not quite sure why I am running into this issue and I have tried a number of other examples to see if I could Identify a difference in initialization and I have been able to make internal loopback function properly but not had luck with external loopback in those either with the same issue, that the port never gets properly initialized.
Does anyone have any ideas about what is incorrect with my configuration or what additional information I can provide that would help in determining the issue? I believe I have the breakout card and loopback cables properly connected. I am less sure about there being some issue related to the silicon revision of the board (I see several suspects in sprz401f.pdf, the TCI6638K2K Silicon Errata). I feel that I could easily have missed some additional configuration step when I was looking over the approach taken in the example.
Any insight is appreciated, thanks.