Part Number:TMS320C6657
Hello Experts,
I read the following document. I'd like to understand the specification and the thought of detailed behavior of the cache coherence protocol. Please give me some advice.
TMS320C66x DSP Cache User Guide (SPRUGY8) : 2.4.2 Cache Coherence Protocol for DMA Accesses to L2 SRAM
3. If the line is cached in L1D, the L2 controller updates the data in L2 SRAM and directly updates L1D cache by issuing a snoop–write command. Note that the dirty bit is not affected by this operation.
In the case, both L1D and L2SRAM are updated to the same value by the snoop-write command. I think this state is Clean, why is not the dirty bit affected? If DMA write access is followed by DMA read access as shown in Figure 2-4, I think that a snoop-read command will be issued, which will lead to a slight delay for the data transfer. Because the dirty bit is still set.
Regards,
Kazu