McAsp ASYNC=0 RX signal delay

Hello,

I want to make a bidirectional I2S transfer between McAsp and an external controller. The external controller is master and I use the McAsp in synchronous mode (ASYNC=0). In SPRUHF4C chapter 13.2.2.2 Receive Clock I can see that RCLK is inverted relating to XCLK. Do I understand it right that the RX signals have to be delayed by half a CLK cycle to be sure to sample it in the middle of a bit?

Best regards