TM4C1294KCPDT: Analog comparator C0+ threshold

Part Number:TM4C1294KCPDT

Is it possible that the PWM module generators MnFaults GPIO inputs when internally OR'd are effecting analog comparators shared C0+ (pin0) or Cn- input threshold levels?

Oddly the voltage trip threshold seems to increase from C0- to C1- by over 200mv and over 500mv C1- to C2- as the MnFault inputs are enabled consecutively. So each analog comparators XOR GPIO output seemingly should be (Open Drain) when a single PWM0 generator can or might internally OR multiple fault sources together. 

Seemingly the fault source OR is necessary so any single MnFault will trip fault or interrupt any GENS part of the OR'd fault structure. This is so any random fault arriving on any MnFault input pin disables the PWMENABLE register in the output control block.  

Tivaware call to OR multiple generators for analog comparators XOR outputs being connected to PWM module MnFault inputs. 

   /* Configure (OR'd) extended fault group-0 interrupt sources for M0Fault pins.
    * Assertion to PWM inactive TFaultMax = 40ns, (24ns+1PWMCLK) */
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_0, PWM_FAULT_GROUP_0,
    							(PWM_FAULT_FAULT0|PWM_FAULT_FAULT1|PWM_FAULT_FAULT2));
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_1, PWM_FAULT_GROUP_0,
    							(PWM_FAULT_FAULT0|PWM_FAULT_FAULT1|PWM_FAULT_FAULT2));
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_2, PWM_FAULT_GROUP_0,
    							(PWM_FAULT_FAULT0|PWM_FAULT_FAULT1|PWM_FAULT_FAULT2));