Part Number:UCC28780
I'm using the Mathcad documents from sluc644. In the "Neutron..." worksheet there is a test to make sure the 40 ns delay T.DPWML_H (plus driver delays) is greater than the actual circuit rise time at the switching node (T.rise_max). The test works fine in the original worksheet, but only because the calculation for C.sw_T (total switch node capacitance) uses a fixed value of 40 pF for C.oss_Q_T (the time-based Coss for the primary switch FET).
I can't find any FETs, GaN or Si, which have this low a time-based Coss. Typical GaN FETs seem to run more like 200 - 300 pF, and that causes the T.DPWML_H test to fail. It is suspicious that the C.oss_Q_T in the worksheet is fixed at 40 pF rather than being voltage-dependent. It's like someone stuck 40 pF in there to make the formula work. This affects other calculations too.
To get around this should I run the UCC28780 with SET = 5V to select a Si switch even though I'm using GaN? Will that provide enough delay on T.DPWML_H and not cause other problems?
Thanks for any help.