Part Number:TMS320F28379D
Hi,
I need to do inter-boards isolated PWM synchronization and synchronize as precisely as possible all the DSPs PWM together on all boards.
The technical reference manual and the datasheet shows that the EXTSYNCOUT is stretched 8 PLLSYSCLK cycles. The datasheet specify the minimum number of cycles for SYNCIN in asynchronous, synchronous and with input qualifier.
The technical reference manual specify the delay from a master ePWM module to a slave ePWM module in TBCLK and EPWMCLK cycles. The technical reference manual depicts ePWM SYNC in the ePWM module time-base waveforms or in its different sub-modules diagrams as being active on the rising edge. These diagrams are functional diagrams, not timing diagrams.
There is no detailed timing diagram for the SYNCIN inputs in the datasheet. :(
There is also no maximum width specified for SYNCIN in the datasheet (obviously needs to be far less than the PWM period itself). Question in original thread was about the trigger edge. I don't know what is the exact meaning of "The synchronization is fixed as active low." in the original thread answer. I need an answer based on the real behavior of the ePWM sync input internally.
If my inter-boards isolated synchronization mechanism is extending the synchronization pulse to a value greater than 8 PLLSYSCLK or if I use any other global synchronization pulse method to send it to all boards at once, how the ePWM modules will align to this pulse (i.e. give detailed timing diagram)?
Is it only edge aligned to the rising edge of the external synchronization pulse (plus some minimal sampling delay like 1 or 2 EPMWCLK if asynchronous in input qualifier) and a long external synchronization pulse will generate one and only one internal synchronization pulse for each external pulses received (as depicted in the functional diagrams in the technical reference manual)?
Thanks
P.S. A short mention in the datasheet about the real internal alignment in ePWM module near the SYNCIN pulse requirement would resolve all this.