Part Number:66AK2H14
Hi,
I have read the SPRUHO3A Serdes user guide document, and was surprised by the restrictions applying to REF_CLK values. Specially given all the MPY/RATE_SCALE facilities available through registers.
For example table 7-1 accepts 125 MHz input frequency for SRIO Serdes while Hyperlink Serdes does not (see table 8-1) , nor 10Gbe serdes.(table 11-1). The most restrictive being PCIe serdes, only accepting 100MHz input frequency (table 10-1).
At same time the document admits that other configurations might exist and that we should refer to a "configuration list" inside TI MCSDK.
Here are the questions :
- Could you please send me the above-mentioned "configuration lists " because I don't know where to find it.
- Are the limitations only due to currently available software, or are they resulting from hardware reasons ? For example how explain that it is not possible to achieve 2.5Gb/s PCIe from a 125MHz input clock, the Fq ratio being so straighforward ?
With best regards,
Bruno