Part Number:AM4379
Hi,
Background
I am using the AM43xx EMIF Tool: Register Configuration Revision 1.0 from the AM43xx EMIF Tools report for a device connected to a single DDR3L at a PLL clock of 303MHz and 16 bit data bus.
Issue
Once the spreadsheet was configured for the system details, DDR3L device timings, and board details, the interface was not working. The issue was found to be related to the READ_LAT[4:0] bits of the EMIF4D_DDR_PHY_CTRL_1 register which was set to '8' when the CAS Latency on the :"Step2-DDR Timings" sheet was set to 6 tCK. Manually updating the READ_LAT value to '9' resulted in a working memory interface.
Question
The TRM description for the READ_LAT bits indicates the EMIF will expect data at reg_read_latency + 3 clock cycles which would result in a READ_LAT setting of '9' when CAS Latency is set to 6 tCK instead of '8'. Is the READ_LAT cell in the EMIF tool using a + 3 or + 2 offset from the CAS Latency setting? Does this need to be updated?
Best Regards,
Mark-