LAUNCHXL-F28379D: Strange MOSI behaviour. It doesn't return to Vcc.

Part Number:LAUNCHXL-F28379D

Hello,

I am trying to communicate my launchpad with Wiznet W5100 chip and i noticed something strange. In my application I am trying to read a byte every second. To read it I have to send OP-code register and dummy data to push my data to read.

It's about MOSI behaviour. It's not returning to level-high every transmission and I think it is reason why data I am reading are not always correct. Here are pictures from my scope:

with 500ms/div:

and with 50 us/div:

As you can see data are sent but I have no idea why mosi aren't returning to idle state after transmission. Here is my code to init SPI (from TI EtherCAT hal for c28xx) and code to send data:

#include "F28x_Project.h"
#include "driverlib.h"
#include "device.h"
#include "PinMux/pinmux.h"

#if CPU_FRQ_200MHZ
#define SPI_BRR        ((200E6 / 4) / 500E3) - 1
#endif

//
// Function Prototypes
//
void InitSpiAGpioPullUps(void);
void ESC_initSPIFIFO(void);
void ESC_writeSPI(void);

uint16_t readval[8];
volatile struct SPI_REGS *SpixRegs;

void main(void)
{
   SpixRegs = &SpiaRegs;

//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
   InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// Setup only the GP I/O only for SPI-A functionality
// This function is found in F2837xD_Spi.c
//
   GPIO_setPinMuxConfig();
   InitSpiAGpioPullUps();
//
// Step 3. Clear all interrupts:
//
   DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE __interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
   InitPieCtrl();

//
// Disable CPU __interrupts and clear all CPU __interrupt flags:
//
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
   InitPieVectTable();

//
// Step 4. Initialize the Device Peripherals:
//
   ESC_initSPIFIFO();

//
// Step 5. User specific code:
//

   SpixRegs->SPITXBUF = (0xF000);  // reset W5100
   SpixRegs->SPITXBUF = (0x0080);
   while(SpixRegs->SPIFFRX.bit.RXFFST < 2);
   readval[0] = SpixRegs->SPIRXBUF;
   readval[1] = SpixRegs->SPIRXBUF;

   uint16_t buffer8bit [4] = {0};
   for(;;)
   {
       ESC_writeSPI(); // read sample register

       DELAY_US(1000*1000);
   }
}

void InitSpiAGpioPullUps(void)
{
    EALLOW;
    // Enable pull-ups on SPISIMO/SPISOMI/SPICLK/SPISTE pins
    GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0;

    // Enable SPISIMO/SPISOMI/SPICLK pins as async
    GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 0b11;
    GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 0b11;
    GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 0b11;
    GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 0b11;
    EDIS;
}
void ESC_initSPIFIFO(void)
{
    uint16_t m;
    EALLOW;

    // FIFO configuration
    SpixRegs->SPIFFCT.all=0x0;              // place SPI in reset
    for(m=0;m<3;m++);
    SpixRegs->SPIFFRX.all=0x2040;           // RX FIFO enabled, clear FIFO int
    SpixRegs->SPIFFRX.bit.RXFFIL = 16;      // Set RX FIFO level
    SpixRegs->SPIFFTX.all=0xE040;           // FIFOs enabled, TX FIFO released,

    // SPI configuration
    SpixRegs->SPIFFTX.bit.TXFFIL = 16;      // Set TX FIFO level
    SpixRegs->SPICCR.bit.SPICHAR = 16-1;     // Character Length  = 8
    SpixRegs->SPICCR.bit.CLKPOLARITY = 0;   // Rising edge
    SpixRegs->SPICTL.bit.SPIINTENA = 1;     // Enabled
    SpixRegs->SPICTL.bit.TALK = 1;          //
    SpixRegs->SPICTL.bit.MASTER_SLAVE = 1;  // Master mode
    SpixRegs->SPICTL.bit.CLK_PHASE = 1;     // Add 1/2-cycle delay of Clk wrt SPISTEA
    SpixRegs->SPICTL.bit.OVERRUNINTENA = 1; // Overrun Interrupt enabled
    SpixRegs->SPISTS.all=0x0000;            // Clear Status bits (TxBufFull,INT, Overrun)

    SpixRegs->SPIBRR.all = 0x63;        // LSPCLK/100
    //ClkCfgRegs.LOSPCP.all = 0x1;            // 0 = sysclk/1 = 200M; 1 = sysclk/2 = 100M
    //SpixRegs->SPIBRR.all=0x001;             // Baud Rate = LSPCLK / (SPIBRR+1) [LSPCLK=SysClk/4 by default=50M]
    SpixRegs->SPIFFCT.all=0x00;
    SpixRegs->SPIPRI.all=0x0020;            // Stop after transaction complete on EmuStop

    SpixRegs->SPIFFTX.bit.TXFFIENA = 0;     // Disable TXFF INT
    SpixRegs->SPIFFRX.bit.RXFFIENA = 0;     // disable RXFF INT


    SpixRegs->SPICCR.bit.SPISWRESET=1;      // Enable SPI

   EDIS;
}

void ESC_writeSPI(void)
{
    SpixRegs->SPITXBUF = (0x0F00);
    SpixRegs->SPITXBUF = (0x1A00);
    while(SpixRegs->SPIFFRX.bit.RXFFST < 2);
    readval[2] = SpixRegs->SPIRXBUF;
    readval[3] = SpixRegs->SPIRXBUF;

    SpixRegs->SPIFFTX.bit.TXFIFO=0;     // Reset Tx FIFO
    SpixRegs->SPIFFRX.bit.RXFIFORESET = 0; //reset the FIFO pointer
    DELAY_US(2);
    SpixRegs->SPIFFTX.bit.TXFIFO=1;     // Reset Tx FIFO
    SpixRegs->SPIFFRX.bit.RXFIFORESET = 1; //reenable the FIFO operation
}

I think it is not regular behaviour of MOSI. I appreciate any help.

Best regards,
Dawid.