Part Number:SN74LVC1G80
I need a 60Hz square wave whose edges are synchronous with zero-crossings of AC mains voltage. My zero crossing detector works fine and generates a clean 120Hz pulse train.
I feed this 120Hz signal into the CLK pin of a 74LVC1G80 "Tiny Logic" D flip flop that is configured as a divide-by-2 counter. The Q-not output (pin 4) of the FF is tied back to the D input (pin 1).
But this beast does not function as a divide by 2. The Q-not output does not wiggle, period.
The TI datasheet for this part shows a complicated implementation of a divide-by-2 counter where an external CPU pin with tri-state capability contends briefly with the Q-not output pin to preset the flip flop to a known state before it begins to divide by 2.
Why is this power ON preset strategy needed? The part's truth table is simple and doesn't hint at the need for a power ON preset.
I don't care about the flip flop's first state at power ON as long as the circuit eventually gets around to dividing my zero-crossing signal by 2.
Thanks.
Jim Olson
Lafayette, IN