Hi,
We are working on debugging a DDR timing issue. We can open up a CCS memory window (CCSv5.3) on the Arm of a DM8148 device. The window is set to the default 32-bit HEX words. We make the window large to show lots of values and then repeatedly refresh the window and now and then we see a value change, nothing is running at that point and the CPU is halted. We then run a simple piece of code that runs in a loop and reads the same region of DDR repeatdly and looks for read failures, we perform 32-bitr reads. We initialize the DDR first with a known ramp sequence. The problem is, we don't see any failures when running code but we do when refreshing a memory window with the CPU halted.
My question is, when we refresh a memory window that's showing 32-bit HEX values, what exeactly does CCS do to read the memory? Is it performing individual 32-bit reads one after another? If so, is there a long delay between reads? Is it trying to burst multiple words somehow like you might get with a DMA? Maybe it's using load double-words? We're trying to determine how our read loop differs from the CCS memory window update.
Thanks