F2802x & F2803x ADC result timing

i use F2802x to do some experimenst. i have two problem:

(1) according to user's guide, in sequential mode / early interupt pulse , the ADC's result can be read after 15 adc clock (can be read at 16th clocks). CPU takes 9 clocks to go into interrupt service routine, and the the actual reading occurs at 6th pipeline phase. In other words, i can get the adc result (1(ECO pulse) + 9(ISR process) + 6(pipeline) = 16) even if the reading instuction is 1st line in ISR?

(2) i usually get the wrong ADC result at the 1st time ADC. (use late interrupt pulse)