RTOS/AM5728: Memory mapping for DSP

Part Number:AM5728

Tool/software:TI-RTOS

Hello TI,

Hello Community,

I would like to use both DSPs for two dedicated network stacks. Each one has two main tasks: Task 1 for network stack and task 2 for controlling and stabilizing network clients. To satisfy the scheduling, the DSPs have to use a cache. I am using TI RTOS (version 3.02.00.05) on both DSPs and I would like to configure my memory in a sustainable way to counteract possible amount of changes or variants in the future. After studying the TI corePac manual and browsing the internet, in one off the TI forums (if I recall correctly) I found a solution to enable the (L2) cache with the help of CSL by calling the following functions:

CACHE_enableCaching(128);
...
CACHE_enableCaching(159);
CACHE_setL2Size(CACHE_256KCACHE);
CACHE_wbInvAllL2(CACHE_WAIT);

Thus, I can reduce my cycle time by 33%. That sounds quite good. But I would like to understand these lines and this approach, respectively.

1. The CACHE_enableCaching(<region>) sets the MAR bits and finally a 16 MB region in DDR3 as cacheable. The argument represents the memory offset, started for example at 0x0_8000_0000. So in my example, I set the following external memory address range (DDR3) as cacheable:
   1. start address: 0x0_8000_0000 + 0x0_7F00_0000 = 0x0_FF00_0000
   2. end address:  0x0_8000_0000 + 0x0_9F00_0000 = 0x1_1F00_0000
   3. size: 0x2000_0000 = 512 MB
      Is this correct?
2. I am using TI RTOS and I would like to avoid the cache configuration in code. Rather, I would like to do this statically in the configuration and memory file. Is this possible? What is the counterpart for the xdc tools? I tried something like

   var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
   Cache.setMarMeta(0x80000000, 0x00100000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE);
   or
   Cache.setMarMeta(0x86000000, 0x0600000, 0xD);

    without any success
3. What is the difference between line 4 (CACHE_setL2Size(CACHE_256KCACHE);) and the command in a .bld-file: l2Mode: "256k"?
4. What does CACHE_wbInvAllL2(CACHE_WAIT) really do?
5. What about L1 Cache? How can I configure this?

Is this all possible without creating or modifying the platform described here or here?

Thanks for your help.

Best regards

Thomas