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RM48L930: SCI/LIN baudrate fine-tuning using 4-bit fractional divider M

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Part Number:RM48L930

Support Path: /Product/Help with Device Selection/

Hello,

The Hercules reference manual (spnu503b.pdf) section 25.2.3 (SCI Baud Rate) states:

The SCI/LIN has an internally generated serial clock determined by the peripheral VCLK and the
prescalers P and M in this register. The SCI uses the 24-bit integer prescaler P value of BRSR register to
select the required baud rates. The additional 4-bit fractional divider M refines the baudrate selection.
In asynchronous timing mode, the SCI generates a baud clock according to the following formula:

SCICLK Freq = VCLK / ( P + 1 + M/16 )

and   Async baud rate =  SCICLK Freq / 16

My application calls for a baudrate of 115700 baud (not 115200), when running at VCLK = 40 MHz.  A value of P = 20 and M = 10 would result in a baudrate of 115607, which is close enough.

My question:  HALCoGen does not expose the M setting when configuring SCI or SCI2.  The ref manual states that M is set via the BRSR register bits 27:24.  But in SCI mode, the HALCoGen SCI.c driver code does not use the BSRS register, it uses the BAUD register.

Is the reference manual incorrect?  In SCI mode, can I fine-tune the SCI baudrate using the 4-bit M field in register BRSR?   How to do it?

thanks,

Keith


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