Part Number:AM3352
Hi there,
I know the data sheet has mentioned the DDR3L layout guidelines, but there are somethings are not clear to me.
Would like to know below information.
1.) Should CLK be controlled as 100 ohm diff pairs?
CK/CKn , UDQS/UDQSn , LDQS/LDQSn
What is max length on CLK?
How about length matching for same pair?
How about length matching for pairs to pairs?
2.) Should address line be controlled as 50 singled ended?
What is max length on address line?
How about length matching for each address line?
How about length matching for address vs clock ? do we need it ?
3.) Should data line be controlled as as 50 singled ended?
What is max length on data line?
How about length matching for each data line?
How about length matching for data vs clock ? do we need it ?
Thanks