Part Number:TMS320F28335
I’m currently working with a third party design which has TMS320F28335. I was investigating 30MHz clock signals and found out that rising and falling edges are not as steep as I expected.
Measured 10% to 90% rise time is 7.2ns so the actual rise time is about 6.2ns. That is, the clock signal is out of DSP specification. Now, I have few questions:
Q1: I didn’t find clear specification how you specify rise time but I assume you mean 10% to 90% rise time. I.e. for 3.0V signal the time is sitting between voltage levels of 0.30V and 2.7V. Is that correct?
Q2: Is 6.2ns rise time already a problem for DSP performance or do you have some safety margins? How big margins do you have? I mean, what would be an ultimate rise time I should never exceed?
(Green arrow shows the clock signal I'm concerned the most)