Part Number:F28M35H52C
Hi, I tried to read data from FPGA through EPI by C28 as fast as it could. As discussed in other threads, the fastest cylce read by EPI could be two EPI clocks in GPIO MODE. So the EPI is configured as following:
EPI clock = 75MHz; MODE = GPMODE; READ2CYCLE = 1; ASIZE =12; DSIZE =16;
C28 clock =150MHz;
The RTW registers remains as default.
When the M3 was initialized, it halted. I checked the behaviour of EPI in C28 using the assembly codes:
....
movl xar1, #_getBuff ; read buffer
movl xar0, #_EPI_ADDR ; 0x30 0000
L1: .loop 16
mov al,*XAR0
mov *XAR1, al
.endloop
rpt #255
|| nop
bf L1, unc
......
Howerver, one reading cylce are almost 10 C28 cycles, equal to 5 EPI Clocks, more than the expected. And I checked the RD (EPI0S29) and CLOCK (EPI0S31) pin using the oscilloscope. There were almost 4 EPI clocks between the RD signals. The question is: Is this behaviour normal? Or, is there any incorrect configuration described above?