Part Number:LMK04828
I am trying to configure the LMK04828 to use the SYSREF clock at the feedback path to PLL2. I am inputting a 100MHz clock on OSCin, bypassing the 2x multiplier and setting the R2 divider to 2. The output of the PLL is going to the SYSREF divider which is set to 30. I have then set the FB_Mux to output SYSREF_DIV and the PLL2_IN_MUX to select FB_Mux and set the N2 divider to 2. In this configuration the PLL will not lock and I do not know why. If I use the same setting but change PLL2_IN to use the N2 Prescaler and set this prescaler to 30 the PLL will lock. Can someone please provide me with the programming steps to configure the part in this way?
I have attached the register settings I am using in the order that I am programming them for reference.
0x138 0x21
0x139 0x00
0x13A 0x00
0x13B 0x1E
0x13C 0x00
0x13D 0x08
0x13E 0x03
0x13F 0x15
0x140 0x03
0x141 0x00
0x142 0x00
0x143 0x11
0x144 0x00
0x145 0x7F
----------- CLKin Control (0x146 - 0x149) ----------
0x146 0x18
0x147 0x0A
0x148 0x0B
0x149 0x0B
------ Reset_Mux and Reset_type --------------
0x14A 0x02
---- 0x14B - 0x152 Holdover -----------------
0x14B 0x32
0x14C 0x00
0x14D 0x00
0x14E 0x00
0x14F 0x7F
0x150 0x03
0x151 0x02
0x152 0x00
--------- PLL1 Configuration (0x153 - 0x15F) ------------
0x153 0x00
0x154 0x01
0x155 0x00
0x156 0x01
0x157 0x00
0x158 0x01
0x159 0x00
0x15A 0x0A
0x15B 0xD4
0x15C 0x20
0x15D 0x00
0x15E 0x00
0x15F 0x0B
-------- PLL2 Configuration (0x160 - 0x16E) ------------
0x160 0x00
0x161 0x02
0x162 0x44
0x163 0x00
0x164 0x00
0x165 0x19
----------- Prog ng registers 0x17C and 0x17D
0x171 0xAA
0x172 0x02
0x17C 0x15
0x17D 0x33
0x166 0x00
0x167 0x00
0x168 0x02
0x16A 0x20
0x16B 0x00
0x16C 0x00
0x16D 0x00
0x16E 0x13
---- -- Misc registers ----------------
0x173 0x00
0x182 0x00
0x183 0x00
----- load SYSREF Divider ----------------
0x143 0xB1
0x143 0x11
0x144 0xFF
0x139 0x03
0x13F 0x15