Part Number:TM4C129XNCZAD
Tool/software: Code Composer Studio
I am having problems when debugging the TivaWare project boot_emac_flash. The project should download a new firmware image via Ethernet.
Breakpoints don't work initially and I can't step through the assembly code. These two issue combined make it impossible for me to see any initial setup code. The code doesn't run properly with optimizations off. I think the issues are caused by the chip running code from SRAM.
Breakpoints for C files can not be set when the code is first loaded. Disabling and enabling a breakpoint will cause it to take effect after the code is allowed to run. I also see the breakpoint take efect if the chip is suspended and resumed, but thos results are intermittent. I know the processor will hit a while(1) loop on line 1776 of bl_emac.c. I set a break point in this loop. Pausing the chip shows it is within this loop. I can single step over the breakpoint. After I resume running, the chip might start hitting the breakpoint . If I pause, disabled and re-enabled the breakpoint, it will break. I do this by unchecking and checking the box in the Breakpoints window. Note to re-create this issue, the dev kit needs to be plugged into a switch. A previous wait looks for network connectivity. before hitting line 1776 of bl_emac.c
Line 257 of bl_startup_ccs.s does not work with the step over or step into commands. Either of those commands seem to act like the command resume running. ProcessorInit is on line 190 of bl_startup_ccs.s. I can set a break point after the label "ProcessorInit " and it will stop, but the process will behave as if "resume running" was clicked if the breakpoint is not set.
With optimizations off, the chip does not go to the function specified by the reset vector. I can see the reset vector is set to 0x16D5 in the memory browser and the disassembly shows ResetISR() at 0x2000016D4, but this point is not hit by the first step over. I think the PC arrives at the wrong function by error (
With optimizations on, ResetISR() is hit by the first step over with optimizations on when the reset vector is 0x0DC9 and ResetISR() at 0x20000DC8
The disassembly window always shows the processor at some 0x2000XXXX address which is why I believe the setup code makes the chip operate from SRAM.
I import the project from TivaWare_C_Series 2.1.4.178. I follow CCS warning to change the compiler from TI v5.2.6 to TI v18.1.1.LTS. CCS is at version 8.0.0.00016. The target hardware is the EK-TM1294XL. The connection is ICDI.