Part Number:TMS320F280049M
Hi,
I have setup TMS320F280049 to drive two switches whose pulses are complementary, have 50% duty-cycle, and have 150ns deadtime between them. The frequency of pulses varies from 50kHz to 1MHz. I am changing the frequency by changing voltage at the ADC input by varying a variable resistor which is connected at ADC input. Reading the ADC register and calculation of the frequency of pulses is performed in fixed frequency ISR which is triggered by ADC End of conversion pulse and updating the PWM registers (TBPRD,CMPA,CMPB) is performed in EPWM1 ISR which is a higher priority interrupt triggered when EPWM 1 CTR=0. EPWM1 interrupt is nested in ADC interrupt. The ADC start of conversion is triggered by CPU TIMER 0 which runs at fixed frequency of 50kHz.
EPWM pulses with 50% duty-cycle are generated by writing to CMPA and CMPB registers independently a level equal to TBPRD/2. EPWMB pulse is then inverted in deadband module to generate a complementary pulse.
There is some other calculation taking place in ADC ISR based on the input voltage, which has nothing to do with the calculation of the frequency, CMPA and CMPB. The total calculation time of ADC ISR is 9.5us and EPWM1 ISR is ~360ns (as only updating of EPWM registers take place in this routine).
The deadtime between the pulses is constant and setup only once during intialization to 150ns.
With this setup, I observed that deadtime between the two pulses was collapsing randomly to <50ns, which means 150ns deadtime was not maintained.
I experimented and observed, that this can only happen if for some reason executed values of CMPA and CMPB are not equal. This should not happen if I am updating both the registers one after the other with a same value =TBPRD/2 in a higher priority interrupt EPWM1 ISR which is nested inside ADC interrupt.
If EPWM1 ISR is higher priority, first all registers should be updated and then the program counter should go back to ADC ISR to calculate the next value of frequency.
I was temporarily able to solve the deadtime collapse issue by setting a flag high when program counter is in ADC ISR and calculating frequency. When flag is high, I do not allow EPWM 1 registers to update in EPWM1 ISR, even though, EPWM1 ISR can still interrupt ADC ISR. Once, calculation is finished, I make flag go low and then EPWM 1 registers can update in EPWM1 ISR. This way deadtime maintained at 150ns.
However, this is a brute force way of solving the issue. I would like a better solution/ suggestion from TI to solve this problem.
Thanks,
Misha