TM4C1231H6PGE: Questions on SSI module within TM4C123

Part Number:TM4C1231H6PGE

Hi all, by reading the data sheet of TM4C123, I am not very clear on how the timing of SSI transmission works and wonder if anyone can clarify a few things here. I am using SSI1 as a SPI host, here is what I am not certain:

1) When will the transmission start? Is is true that the data will be transmitted out as long as the transmission FIFO is NOT empty and SSE bit in SSICR1 is set?

2) Does the transmit/receive logic within SSI module determine all SPI bus timing timing ? For example, when sending data out, it will drive the SSI1Fss pin to low to serve as the Chip Selecting, and enable the SSI1clk pin to send out clocks?

3) If 2) is true, when reading the data from the salve, how does transmit/receive logic know when the slave finishes the data sending so that it knows how long it should keep SSI1Fss as low?

Thanks

Richard