TM4C123GH6PGE: Why does the SSI rx fifo need to be flushed for every transaction?

Part Number:TM4C123GH6PGE

Hi,

Hopefully a simple question and apologies if it has been answered somewhere else on the forum, but I couldn't find it.

SSI1 is configured as master and the function below sends txlen bytes from txdata buffer and stores the received bytes in rxdata buffer.

The function works perfectly! However if I miss out the line which flushes the rx fifo, the next time the function is called the received data contains some bytes from the previous exchange and I would like to understand why. Anyone know?

void SSI1exchange(uint8_t txlen, uint32_t *txdata)
{
	uint32_t flush;
	static uint32_t rxdata[256];
	
	while(ROM_SSIDataGetNonBlocking(SSI1_BASE, &flush)) ;	//flush SSI1 rx fifo
	
	for(i=0;i<txlen;i++) {
		ROM_SSIDataPut(SSI1_BASE, txdata[i]);	//send bytes out of SSI1
		ROM_SSIDataGet(SSI1_BASE, &rxdata[i]);	//store the bytes coming back
	}
}