Part Number:TMS320C6678
Tool/software:TI-RTOS
I have a DSP C6678 that I need to configure as the root complex (RC) and it will connect to an FPGA configured as a single endpoint (EP). I only have one lane and it will be configured for Gen 1 (2.5 Ghz). The DSP (RC) will always initiate transfer for read/writes to the FPGA (EP). The FPGA will never initiate a read/write request.
I am trying to get the sample program provided with the pdk_c667x_2_0_0 for the c6678 to work. I have compiled the sample code that uses the driver located in the pdk at ti/drv/pcie/example/sample/src/pcie_sample.c. I have linked to the driver in ti/drv/pcie/lib/c6678/c66/ti.drv.pcie.c6678.ae66. In the main function, pcie(), the code gets to the function pcieWaitLinkUp(), where it polls forever looking for the LTSSM state to reach LO (0x11). This can be seen in DEBUG0 (0x2180 1728) LTSSM_STATE field.
The main problem is the PCIe LLD API calls for Pcie_readRegs and Pcie_writeRegs do not seem to be working. Using the sample when I try to disable link training in the function call pcieLtssmCtrl(), the function succeeds with a return value of pcie_RET_OK, but I can't disable or enable the link training. I'm looking at 0x21800004 for the LTSSM_EN bit to change.
Have I configured something wrong with the sample project for the C6678?