Part Number:TMS320C6746
Hello,
I want to use TMS320C6746's parallel port at 80 MHz data rate in SDR receive mode. If you look at TMS320C6746's datasheet, Table 6-103 (page 205), it seems like the maximum allowed data clock for UPP is 75 MHz (period of 13.33ns), and that would be the external source-synchronous clock I'd need to apply to the UPP clock pin.
I think this limitation is not imposed by hardware IO buffers, as the external 2x transmit clock pin can go to 150 MHz, and at first sight I see no reason for the UPP receive clock not being able to phisically support that speed.
Then, when you read the UPP section of the datasheet, it says that the UPP data clock is limited to 1/2 of the UPP peripheral clock, which is itself half of the DSP core, so the UPP clock is limited to DSP core clock/4. If you run the DSP at 300 MHz, then UPP clock is max. 75 MHz. If you run it at 100 MHz, max UPP clock is 25 MHz and so on. I understand that this is a hard frequency limit as UPP's peripheral clock needs to be 2x data clock so that external data clock can be asynchronous to the internal peripheral clock.
So, we apparently have two limits:
1-UPP data clock needs to be <= DSP clock/4
2-UPP data clock needs to be <= 75 MHz
TMS320C6746's first silicon revisions topped at 300 MHz DSP clock, but current revisions can go to 375 or 456 MHz. As the 75 MHz UPP clock limit doesn't seem to me being hardware-related, was this limit related to the DSP clock/4 limit and it hasn't been updated to reflect new maximum DSP clock speeds in the new silicon revision?
In other words, is the limit truly 75 MHz or can I run it to DSP clock/4, enabling me to go up to potentially 114 MHz? (456/4)?
Thanks,
David
