PROCESSOR-SDK-AM65X: Kernel hang at dynamic shared memory/OP-TEE

October 15, 2019, 1:35 pm

≫ Next: ADS1115-Q1: Leakage on Analog Inputs

≪ Previous: CCS/AM6548: Example SYSBIOS project for AM6548 ARM A53 won't build

Part Number: PROCESSOR-SDK-AM65X

We are testing the Linux 06.00.00.07 release for the AM65x processor on our custom board, which is very close in design to the AM65 EVM. Using the prebuilt U-Boot, Linux image, and DTB for the AM65 EVM on our custom board, we see that it hangs fairly early in the boot process. These are the last lines we see output on our board:

[ 0.000005] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns

[ 0.008695] Console: colour dummy device 80x25

[ 0.013248] console [tty0] enabled

[ 0.016729] bootconsole [ns16550a0] disabled

When we run the identical executables and DTB on the EVM we see the same four lines at the same point in the boot process, followed by this line:

I/TC: Dynamic shared memory is disabled

At which point the Linux kernel restarts, but this time the "I/TC: Dynamic shared memory is disabled” is not output and Linux boots through to the Arago command line.

We are obviously somewhat suspicious that the EVM performs a restart at pretty exactly the same place the Linux kernel hangs on our board. Also, the “I/TC” message output on the EVM is an indication that this is being output from the OP-TEE trusted execution environment. As a result, we’re wondering if it’s possible our board is hanging at this point because of a TEE-related issue. Questions:

1) Can you tell us why the Linux kernel running on the EVM is restarting following the "I/TC: Dynamic shared memory is disabled” message?

2) Is it possible our custom board is hanging at this point because of a TEE-related issue?

3) Can you identify what we might have missed related to the TEE that could be causing this hang on our custom board?"

↧

ADS1115-Q1: Leakage on Analog Inputs

October 15, 2019, 1:47 pm

≫ Next: Compiler/TM4C123GE6PZ: Problems on running a program from a different address with bootloader when external interrrupt handlers are

≪ Previous: PROCESSOR-SDK-AM65X: Kernel hang at dynamic shared memory/OP-TEE

Part Number: ADS1115-Q1

Hi Team,

I am looking into the leakage current of ADS1115/ADS1118-Q1 and found the discussion in this thread very useful - http://e2e.ti.com/support/data-converters/f/73/t/688431

When looking into the input current at analog ports, there is always a current to charge the sampling capacitance. Since these 2 devices integrates PGA then looking into the analog input impedance should be sufficient for application design. Just to clarify, the common-mode input impedance here follows the op amp traditions, which refers to either input to GND but not both input to GND, right?

For the analog mux, like ADS1115 datasheet figure 25, there are always concern from customer regarding the leakage of clamping structure. How to properly address the leakage current of this ESD structure in the application design? More precisely, what would be the typical leakage current of the mux inputs?

Thanks for your help.

Peiheng.

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Compiler/TM4C123GE6PZ: Problems on running a program from a different address with bootloader when external interrrupt handlers are

October 15, 2019, 1:51 pm

≫ Next: ADS1263: Using OP Amp to drive ADS1263

≪ Previous: ADS1115-Q1: Leakage on Analog Inputs

Part Number: TM4C123GE6PZ

Tool/software: TI C/C++ Compiler

Hello everyone,

I am having problems running an application with a bootloader on a custom TM4C123 board.

The application has 2 interrupt handlers present that is linked on startup.ccs file.

When the application runs from appbase = 0x00000000 there is no problems and these interrupt handler are called without issue.

However, when I change the appbase to 0x00002800 on the cmd file even though the map file shows correct offset and addresses for the symbols of the handlers they are not called

and the program jumps to an address where there is no user application(0x20009002).

Does anyone encountered similar problems similar to this?

Thanks.

The cmd file is the following:

--retain=g_pfnVectors

#define APP_BASE 0x00002800
#define RAM_BASE 0x20000000

MEMORY
{
FLASH (RX) : origin = APP_BASE, length = 0x0003d800
SRAM (RWX) : origin = RAM_BASE, length = 0x00008000
}

SECTIONS
{
.intvecs: > APP_BASE
.text : > FLASH
.const : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH

.vtable : > RAM_BASE
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM
}

__STACK_TOP = __stack + 512;

The symbols are shown like this:

GLOBAL SYMBOLS: SORTED BY Symbol Address

address name
------- ----
00000200 __STACK_SIZE
00002800 g_pfnVectors
...
...
00003e3f Timer1BIntHandler
00003e53 Watchdog0IntHandler

↧

ADS1263: Using OP Amp to drive ADS1263

October 15, 2019, 1:53 pm

≫ Next: CCS/LAUNCHXL-CC1352P: Mem allocation error when logging enabled : #10099-D: program will not fit into available memory. run placement with alignment fails for section ".bss" size 0x3b95

≪ Previous: Compiler/TM4C123GE6PZ: Problems on running a program from a different address with bootloader when external interrrupt handlers are

Part Number: ADS1263

Hello,

I am using the ADS1263 and had a question. If using an op amp to drive it, same power supplies, is it a good idea to place a resistor between op amp output and ADC input. We do have filtering about the op amp. I am more wondering, if the op amp goes to rail, although as stated all parts on the same supply, is there some overdrive possible with internal ESD diodes.

Thanks,

Adam

↧

CCS/LAUNCHXL-CC1352P: Mem allocation error when logging enabled : #10099-D: program will not fit into available memory. run placement with alignment fails for section ".bss" size 0x3b95

October 15, 2019, 2:01 pm

≫ Next: MSP430FR6047: Working with CC112x high performance transceiver

≪ Previous: ADS1263: Using OP Amp to drive ADS1263

Part Number: LAUNCHXL-CC1352P

Tool/software: Code Composer Studio

I am running into a memory allocation error when trying to enable logging for my CCS project. I am able to build my project without logging, but when I change the following lines in the release.cfg file in tirtos_builds_CC1352P1_LAUNCHXL_release_ccs, I get a memory allocation error.

release.cfg:

/* ================ ROM configuration ================ */

/*

 * To use BIOS in flash, comment out the code block below.

 */

//var ROM = xdc.useModule('ti.sysbios.rom.ROM');

//ROM.romName = ROM.CC13X2;



BIOS.logsEnabled = true;



/* Logging config */

var LoggingSetup = xdc.useModule('ti.uia.sysbios.LoggingSetup');

/* Enable CPU Load logging */

LoggingSetup.loadLogging = true;

/*

 *  Enable Task, Swi, and Hwi Load logging. This allows the Idle Task

 *  usage to make more sense. Otherwise Hwi and Swi load is factored into

 *  each task's usage.

 */

LoggingSetup.loadTaskLogging = true;

LoggingSetup.loadSwiLogging = true;

LoggingSetup.loadHwiLogging = true;

Previously, I was able to enable CPU logging in another project by making these changes to the release.cfg file. Now when I try to build this particular project, I get :

<Linking>
"../CC1352P1_LAUNCHXL_TIRTOS.cmd", line 107: error #10099-D: program will not fit into available memory.  run placement with alignment fails for section ".bss" size 0x3b95 .  Available memory ranges:
   SRAM         size: 0x14000      unused: 0x4ea8       max hole: 0x34e0    
error #10010: errors encountered during linking; "../../bin/ia_aac_lc_enc_cm4_eval_rel_pkg.out" not built
 
>> Compilation failure
makefile:178: recipe for target '../../bin/ia_aac_lc_enc_cm4_eval_rel_pkg.out' failed
gmake[1]: *** [../../bin/ia_aac_lc_enc_cm4_eval_rel_pkg.out] Error 1
gmake: *** [all] Error 2
makefile:171: recipe for target 'all' failed

I tried going into the CC1352P1_LAUNCHXL_TIRTOS.cmd file, and changing the size of RAM. The program built, but when I ran it in debug mode, it never stopped at main for me to continue running through the code, so I thought it must be a runtime error.

Is the issue that the holes of allocation are not big enough for the .bss segment specifically? In the error, It does say that unused space in the RAM is 0x4ea8, and 'max hole size' is 0x34e0, but the size of my .bss section is 0x3b95. Is there a way to rearrange space so that it can fit?

I tried going into Project Properties -> ARM Linker -> Basic Options and changing heap and stack size, but this did not help.

I also tried to increase the optimization level, which was at 0. Up to 3, I had the same error, and at 4, I had a #10192 linktime optimization error.

Here is my memory allocation window :

Please advise what further steps I should take to solve this issue.

Warm regards,

Samyukta

↧

MSP430FR6047: Working with CC112x high performance transceiver

October 15, 2019, 2:06 pm

≫ Next: TFP401A-EP: Package/Footprint Dimensions Questions

≪ Previous: CCS/LAUNCHXL-CC1352P: Mem allocation error when logging enabled : #10099-D: program will not fit into available memory. run placement with alignment fails for section ".bss" size 0x3b95

Part Number: MSP430FR6047

Hi,

I would like to know if I could use the wM-Bus stack combining MSP430FR6047 with CC112x transceivers, and if it would be free-of-charge" and "royalty-free", as with others modules.

As said on this link, "The stack is provided “free-of-charge” and royalty-free when used with CC1310 and CC1350."

Also "NOTE: Multiple other TI hardware platforms, including the two-chip solution of the MSP430 + CC112x and CC120x high performance transceivers are also supported, specifically the 868 and 169 MHz bands."

https://www.ti.com/tool/WMBUS

↧

TFP401A-EP: Package/Footprint Dimensions Questions

October 15, 2019, 2:07 pm

≫ Next: LM5118: Buck-Boost Converter Dying

≪ Previous: MSP430FR6047: Working with CC112x high performance transceiver

Part Number: TFP401A-EP

Team,

What is the EXACT recommendation for creating the footprint specifically the center plane copper and solder mask dimensions?
What is the EXACT paste aperture recommendations for 4 mil, 5 mil and 6 mil foils for the center plane paste deposit?
What is the exact dimension (Height) from the bottom of the perimeter lead foot to the thermal pad on the bottom of the component? I’m aware that the thermal pad on the component is recessed into the epoxy and that the results in additional height above the plane of the perimeter leads.

We are trying to minimize the post reflow voiding.

Thank you.

↧

LM5118: Buck-Boost Converter Dying

October 15, 2019, 2:10 pm

≫ Next: BQ40Z80: What MCU is recommended for use with the bq40z80? Something that has a well documented and frequently used SMBus capability.

≪ Previous: TFP401A-EP: Package/Footprint Dimensions Questions

Part Number: LM5118

Hello,

I am building a supply that tops off a 940uF capacitor bank at an adjustable ~52.5V

I was able to to get the circuit working but after unplugging/plugging in the 40v input the LM5118 would shut down and stop regulating. The EN pin is tied directly to the Vin.

I am waiting on more LM5118 to do more testing since I burned the first 5.

Any idea what may be wrong based on the circuit?

Best,

-Danny

This the is WEBench circuit that I based my design on:

This the circuit that I have designed and implemented on PCB.

This is the PCB Layout:

↧

BQ40Z80: What MCU is recommended for use with the bq40z80? Something that has a well documented and frequently used SMBus capability.

October 15, 2019, 2:12 pm

≫ Next: LMX2592: What is the function of pin 30 on this device? Can a lock problem be related to it?

≪ Previous: LM5118: Buck-Boost Converter Dying

Part Number: BQ40Z80

Hello Team,

I am having difficulties getting SMBus to work with STM32 boards, do you have a recommended MCU for SMBus communication with the bq40z80?

Thank you,
Joe

↧

LMX2592: What is the function of pin 30 on this device? Can a lock problem be related to it?

October 15, 2019, 2:15 pm

≫ Next: PROCESSOR-SDK-AM57X: matrix_browser plays h264 videos, but no GPU encoding.

≪ Previous: BQ40Z80: What MCU is recommended for use with the bq40z80? Something that has a well documented and frequently used SMBus capability.

Part Number: LMX2592

Hello gurus,

The LMX2592EVM schematic shows pin 30 connected to GND through a resistor. However, according to both LMX2582 (shown in the schematic) and LMX2592 this pin is NC. Does it have a purpose?

The reason I am asking is because I am debugging a 3rd party board that uses LMX2592 as a clock synthesizer and I found that it never locks properly. The same configuration file loaded on LMX2592EVM works fine. There is a difference in the loop filters but I don't believe that to be a problem. Other than that and the pin 30 I can't see any obvious differences in the designs.

Thanks,
/Mikhail

↧

PROCESSOR-SDK-AM57X: matrix_browser plays h264 videos, but no GPU encoding.

October 15, 2019, 2:17 pm

≫ Next: CC1125: Self Calibration

≪ Previous: LMX2592: What is the function of pin 30 on this device? Can a lock problem be related to it?

Part Number: PROCESSOR-SDK-AM57X

I am using ruby on rails locally on the system.

I am trying to play demo video via matrix_browser. Everything works, except the browser

does not use GPU to decode the videos. CPU usage goes up sometimes to 100%.

Chromium only plays ogg format, and it does not seem to use GPU neither.

I know that gstreamer plays these files but I do not know how to invoke the browser to use playbin to play videos.

↧

CC1125: Self Calibration

October 15, 2019, 2:21 pm

≫ Next: [FAQ] Isolated gate driver FIT rates

≪ Previous: PROCESSOR-SDK-AM57X: matrix_browser plays h264 videos, but no GPU encoding.

Part Number: CC1125

Hello,

My customer has a few questions on the CC1125 that I was hoping to get some help with. They are trying to understand the theory behind specific snippet in 9.14.1 of the user's manual regarding adjacent channel selectivity and how it can be enhanced by setting the FS_CHP register to 0x0C.

"This suggests that a manual “Override” of the Charge Pump Self Calibration is required to achieve optimum phase noise.

I’m curious to know why the self-cal is not optimum
what affect setting FS_CHP register to 0x0C has on the Charge Pump Current
how that impacts the ASIC LO phase noise profile.

Any information you can share in this regard would be greatly appreciated."

Thank you!

↧

[FAQ] Isolated gate driver FIT rates

October 15, 2019, 2:23 pm

≫ Next: LAUNCHXL-CC1350: Simple_peripheral example won't run

≪ Previous: CC1125: Self Calibration

Hello,

We are in the process of adding the FIT rates for our isolated gate drivers to our on-line tool, available at: https://www.ti.com/quality/docs/estimator.tsp

In the meanwhile, below are the FIT rates for our isolated gate drivers from TI.

The following failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested, therefore, it is not recommended to compare failure rates.

Device	FIT
UCC21750-Q1	0.4
UCC23313	0.4
UCC21540A	0.6
UCC21732-Q1	0.4
UCC23511	0.4
UCC5390-Q1	0.4
UCC20225A-Q1	0.6
UCC20225-Q1	0.6
UCC21530	0.6
UCC21530-Q1	0.6
UCC21750	0.4
UCC21710-Q1	0.4
UCC21540	0.6
UCC21541	0.6
UCC21220A	0.6
UCC23513	0.4
UCC21222	0.6
UCC21222-Q1	0.6
UCC21220	0.6
UCC21520-Q1	0.6
UCC5350	0.4
UCC5390	0.4
UCC5310	0.4
UCC5320	0.4
UCC20225	0.6
UCC21225A	0.6
ISO5852S-EP	0.5
UCC20520	0.6
UCC21521	0.6
ISO5451-Q1	0.5
ISO5452-Q1	0.5
ISO5851-Q1	0.5
ISO5852S-Q1	0.5
UCC21520	0.6
ISO5452	0.5
ISO5852S	0.5
ISO5451	0.5
ISO5851	0.5

If you have further questions, please start a new thread and we will assist you.

↧

LAUNCHXL-CC1350: Simple_peripheral example won't run

October 15, 2019, 2:29 pm

≫ Next: BQ21061: Capacitors needed on VINLS and LS/LDO if disabled?

≪ Previous: [FAQ] Isolated gate driver FIT rates

Part Number: LAUNCHXL-CC1350

I'm trying to get the simple_peripheral example code to run on the CC1350 LaunchPad (rev 1.3). I've built and loaded the app and stack using CCS, but when I run the execution never makes it to SimpleBLEPeripheral_taskFxn. Here is where I'm getting the app and stack:

C:\ti\simplelink\ble_sdk_2_02_01_18\examples\cc1350lp\simple_peripheral\ccs

↧

BQ21061: Capacitors needed on VINLS and LS/LDO if disabled?

October 15, 2019, 2:37 pm

≫ Next: CC2540: Current leakage through SPI port's MISO pin because of Tri-State

≪ Previous: LAUNCHXL-CC1350: Simple_peripheral example won't run

Part Number: BQ21061

We will not be using, and will thus be disabling via I2C register setting, the LS/LDO function of the BQ21061. Do we still need to attach capacitors to those two pins, or can we save the money and leave them unconnected?

Thanks,
Scott

↧

CC2540: Current leakage through SPI port's MISO pin because of Tri-State

October 15, 2019, 2:39 pm

≫ Next: SN74LVC257A: A_L/B direction line floating

≪ Previous: BQ21061: Capacitors needed on VINLS and LS/LDO if disabled?

Part Number: CC2540

We are seeing a current leakage via SPI port's MISO pin (Master Input Slave Output) of CC2540 chipset. In our application, the CC2540 chip is Master and Bosch's BMA250E Accelerometer is Slave.

When probed the MISO pin via scope, we observed a leakage current as it is set to tri-state by default. By adding a pull-down resistor on this line/pin, the leakage current is no more observed. Since this is happening in a production unit and it cannot be modified, we tried to do a software workaround - configured MISO pin as 'GPIO' on BLE Micro Application (since it is an input to BLE MIcro) and kept the other 3 lines of SPI - MOSI, CS, Clock PINs to 'Peripheral' mode. All the pins on Port-1 are configured for 'Pull-Down'.

Looks like, this setting has resolved the issue when observed via scope and also we were able to read data with no issues from Slave device. Is configuring MISO to GPIO a valid option and have no side effects?

Can someone from TI help us if this is okay to do? This unit is battery powered and leakage current is not acceptable. Any guidance in this work-around is highly appreciated.

↧

SN74LVC257A: A_L/B direction line floating

October 15, 2019, 2:50 pm

≫ Next: CC1310: Issue reading RSSI using CMD_RX_TEST

≪ Previous: CC2540: Current leakage through SPI port's MISO pin because of Tri-State

Part Number: SN74LVC257A

Hi Team,

My Customer has an old design using a SN74LVC257APW. The A_L/B direction line is floating. Does the part have a pull-down or pull up internally? Is it OK to float this signal? Does the part always behave the same way?

We know that unused input pins must not be left floating and must be tied to GND or VCC, whichever makes more sense or is more convenient or depends on the function of the device.

Looking forward to your input.

Regards,
_Renan

↧

CC1310: Issue reading RSSI using CMD_RX_TEST

October 15, 2019, 2:57 pm

≫ Next: SN65LVDS33-EP: Max Frequency and Fail Safe Circuit

≪ Previous: SN74LVC257A: A_L/B direction line floating

Part Number: CC1310

Hi,

I have read all the posts I could find regarding measuring RSSI by itself but have not been able to get it

to work correctly. My goal is to just read RSSI in a loop looking for energy at 915 MHz.

The code I am using is as follows:

rfc_CMD_RX_TEST_t RF_cmdRxTest =
{
    .commandNo                = CMD_RX_TEST,
    .status                   = 0x0000,
    .pNextOp                  = 0,
    .startTime                = 0x00000000,
    .startTrigger.triggerType = TRIG_NOW,
    .startTrigger.bEnaCmd     = 0x0,
    .startTrigger.triggerNo   = 0x0,
    .startTrigger.pastTrig    = 0x0,
    .condition.rule           = COND_NEVER,
    .condition.nSkip          = 0x0,
    .config.bEnaFifo          = 0x0,
    .config.bFsOff            = 0x1,
    .config.bNoSync           = 0x1,
    .endTrigger.triggerType   = TRIG_REL_START,
    .endTrigger.bEnaCmd       = 0x0,
    .endTrigger.triggerNo     = 0x0,
    .endTrigger.pastTrig      = 0x0,
    .syncWord                 = 0x930b51de,
    .endTime                  = 0
};

bool checkCs(int8_t rssiThreshold, uint32_t timeout, int8_t *recvdRssi)
{
     RF_cmdRxTest.endTime = MSEC_TO_RAT_TICKS(timeout);
     /*
      * Send the cmd
      */
     RF_runCmd(rfHandle, (RF_Op*)&RF_cmdRxTest, RF_PriorityNormal,
                NULL, 0);

     int8_t rssi = 0;
     while((rssi == -128) || (rssi == 0))
     {
         rssi = RF_getRssi(rfHandle);
     }

     *recvdRssi = rssi;

     return(true);
}

The code gets stuck in the while loop since the RSSI value being read is never valid.

I was able to get code using CMD_PROP_CS working fine but was not able to read the RSSI

detected.

I don't have any code to place the radio in continuous RX mode. Do I need to do that?

↧

SN65LVDS33-EP: Max Frequency and Fail Safe Circuit

October 15, 2019, 2:57 pm

≫ Next: SN74LVT8996: BSDL file

≪ Previous: CC1310: Issue reading RSSI using CMD_RX_TEST

Part Number: SN65LVDS33-EP

Original details: 2 questions on the SN65LVDS33-EP (i.e. SN65LVDS33MDREP), Quad LVDS Diff Line Rx

1. I am using this part to convert a differential LVDS 100 MHz clock to TTL for a frequency measurement on a scope. Can you tell me what is the maximum Frequency that can be supported by this 400 Mbps device? If this device cannot support a 100 MHz clock input, is there any other equivalent device LVDS/LVTTL that supports a higher bit rate?

2. With regards to the Fail Safe circuit, the datasheet implies that it will detect if both inputs are missing, but it is not clear if it will detect only 1 input missing? Can you please tell me if this device will detect only 1 of the 2 inputs missing with no external circuitry? If not, can you suggest any external circuitry that will help detect 1 of the 2 inputs missing. I do not want any false PASSES because of a missing input due to noise.

↧