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DLPNIRSCANEVM: DLP NIRscan MicroSD Image for Windows

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Part Number:DLPNIRSCANEVM

Dear Support Team!

Im an owner of a DLP NIRscan spectroscopy. The current firmware version is 1.0, but I want to update it to the latest 3.1 firmware but I'm having issues finding the software. According to the guide( page 41 C.1 part), a file has to be located on the webpage DLP NIRscan MicroSD Image for Windows. Ive made a deep research but I haven't find it. Could you please provide the MicroSD image please? Without the file the update can't be made.

Best regards,

Siket Zoltán


PGA450Q1EVM: RS232 communication interface

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Part Number:PGA450Q1EVM

Hi there,

I am working with the PGA450Q1EVM REV-C (including TI GER-A board and Murata transducer). I got familiar with the GUI and I am able to get range profiles from it. In order to test live feedback and set up a driver for the board, I am now trying to interface with the EVM using UART (RS232). However, I do not get any answer back from the PGA450 when sending command 0 (or any command for that matter).

I am following instructions from PGA450Q1EVM-S User's Guide and TIDA-00151 UART Demo Instructional (Rev. B).

Here are the steps I follow:

0) Connections:
    a) Connect EVM board to 12V power supply
    b) Connect USB cable from laptop to TI GER-A board (the TI GER board is connected to the EVM from the communication PCB)
    c) Connect UART-to-USB cable from laptop to RS232 port on the EVM board

1) Program DEVRAM to use UART demo firmware
    I follow the steps from section 2.2.1 (step 1 to 10) with Q1_TIDA-00151_Rev2_7_DEVRAM-UART.hex from TIDA-00151 UART & LIN Demo Firmware for PGA450-Q1 v2.4 (Rev. D) (note that the link says v2.4 but the .hex inside is rev 2.7)
    The output reads DEVRAM Verification Successful
    I do not disconnect power or any other cables. However I switch back micro controller to ACTIVE in the ESFR tab (is this step missing from the guide?).

At this point I assume that the PGA450 will respond to UART commands.

2) Sending/Receiving commands through UART
    a) Using Hercules Setup Utility, I send command 0 (0x00, 0x55, 0x00, 0x00) as in the related question post. My EEPROM 0x1F address reads 00 so since my sensor address is 0 I send (0x00, 0x55, 0x00, 0x00) as opposed to (0x00, 0x55, 0x01, 0x00)
    b) There is no output back from the EVM board... I tried with other sensor addresses as well. I also notice that the modem lines CD and RI are not green as in the posts from the related question.

3) Check UART communication through GUI
    a) I also tried checking UART through the GUI but I am confused about step 4 (p.7) since I have the EVM and not EVM-S. Instead I assume connections are already done and do not touch the hardware.
    b) Other steps go well but when I type in the command, hit Tx and then Rx, the Rx queue reads exactly the Tx sent...

Any feedback or ideas on how to solve 2 and 3?

PS: I checked the cable by shorting Txd and Rxd and confirmed that I read back what was sent (using Hercules Setup Utility) as expected.

TIDA-01465: Firmware for both the FDC2214 and MSP340

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Part Number:TIDA-01465

Hello,

The firmware for either the FDC2214 and the MSP340 is not provided for the reference design TIDA-01465 Capacitive Frost or Ice Detection Reference Design. Can you please provide it? I am currently assembling one and need the firmware for it. The engineer who designed this is Richard Wang.

Thank you.

TM4C1294KCPDT: Enable XDS200 User CDC serial port output

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Part Number:TM4C1294KCPDT

I am really puzzled. XDS200 installs a CDC driver

"XDS2xx User CDC Serial Port"

But there is NO DOCUMENTATION I could find regarding the pinout on the 19-in connector. Spectrum Digital "Quick Start Guide" is no help, nor is TI Wiki and I didn't find any additional information.
Is the UART just a generic feature of the IP inside of the emulator and not pinned-out?

LOG112: Odd "oscillation" in Vlog output voltage at lower current levels (

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Part Number:LOG112

I'm presenting this problem, not so much for troubleshooting our new design, but in hopes that someone may have seen this issue before.

 

We are using the LOG112 to measure the return current of a high voltage (3.5kV) power supply.  I2 is the reference and is set to 1 uA (2.5Mohm off the 2.5V reference output).  I1, the measured current, ranges from 1 nA to 3.5 mA.

The circuit is powered by an isolated ±12VDC power supply.  The circuit’s return (“ground”) is floating as the return current being measured needs to return to the HV transformer’s return leg which, itself, is floating with respect to system, chassis, ground).

The problem is an odd ‘oscillation’ of the log output voltage that occurs when the startup current to be measured is below about 400 nA.  The ‘oscillation’ goes away if the measured current is raised to 5 uA; the current can then be lowered down into the low nanoamps (10 nA) without the ‘oscillation’ returning; an odd hysteresis.

‘Scope images show this is NOT a typical feedback oscillation, but an odd asymmetrical ramp waveform (fast rise, slow decay) that begins as a small ripple and then progresses to all-out negative rail square-wave swing over 10-30 seconds.  Depending on severity the frequency varies from the tens of Hertz to hundreds of Hertz.

If the measure current at start up is low, i.e. below 100 nA, this happens immediately; if the measure current is close to the threshold (say, 400 nA), the output starts out stable, then a small ripple develops (100 mV), and may not even progress to the square wave.

 

Any help appreciated!

ADS1263EVM-PDK: ADS1263EVM-PDK negative rail issue

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Part Number:ADS1263EVM-PDK

Hi,

I am having an issue with the evaluation board ADS1263EVM-PDK and the ADCPro software. The evaluation card is us to make a proof of concept for a medical device. There is three electrodes that are connected to IN2, IN3 and GND terminals.

Each time I use the electrod and sampling some data like my heart beat, I am always getting a PGA negative rail fault even if the data is between the PGA rails.

The evaluation card is supply in bipolar (±5V) and the internal reference is used.

The ADCPro is setup for sampling AIN2 and AIN3. The PGA Gain is set to 1V/V.

The sampling data magnitudes are between 3.9mV and 4.7mV.

If I use a signal source, I am able to sample a DC signal from -2.2V to +2.2V without the negative rail error.

I have attached the sampled heart beat signal exported to an excel file.

Any idea?(Please visit the site to view this file)

Thanks

Olivier Bergeron

TIDA-01022: TIDA-01022

MSP432P401R: How do I debug this code?

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Part Number:MSP432P401R

I was given some code to fix.  It sets the clock options on the MSP432P401R

The code I am working on is in the I2C, but before I got there it got hung in this routine. 

void CLK_Init(void)
{
  PJ->SEL0 |= BIT0 | BIT1;                // set LFXT pin as second function

  CS->KEY = CS_KEY_VAL ;                  // Unlock CS module for register access
    
  CS->CTL0 = 0;                           // Reset tuning parameters
  CS->CTL0 = CS_CTL0_DCORSEL_3;           // Set DCO to 12MHz (nominal, center of 8-16MHz range)

  CS->CTL2 |= CS_CTL2_LFXT_EN;            // LFXT on

  // Loop until XT1, XT2 & DCO fault flag is cleared
  
  do
  {
     // Clear XT2,XT1,DCO fault flags
     CS->CLRIFG |= CS_CLRIFG_CLR_DCOR_OPNIFG | CS_CLRIFG_CLR_HFXTIFG |
               CS_CLRIFG_CLR_LFXTIFG | CS_CLRIFG_CLR_FCNTLFIFG;
     SYSCTL->NMI_CTLSTAT &= ~ SYSCTL_NMI_CTLSTAT_CS_SRC;
  } 
  while ((SYSCTL->NMI_CTLSTAT | SYSCTL_NMI_CTLSTAT_CS_FLG)
            && (CS->IFG & CS_IFG_LFXTIFG)); // Test oscillator fault flag

    // Select ACLK as LFXTCLK
  CS->CTL1 &= ~(CS_CTL1_SELA_MASK) | CS_CTL1_SELA_0;
  CS->KEY = 0;                            // Lock CS module from unintended accesses
}

I know by single stepping through this code that it is stuck in the do while() loop. 

I am using the IAR compiler, but when I try to watch 
SYSCTL->NMI_CTLSTAT   Unknown or ambiguous symbol
SYSCTL Unknown or ambiguous symbol
SYSCTL_NMI_CTLSTAT_CS_FLG Unknown or ambiguous symbol
CS Unknown or ambiguous symbol
CS->IFG Unknown or ambiguous symbol
CS_IFG_LFXTIFG Unknown or ambiguous symbol

So I start looking through the msp432p104r.h file to try to figure what the heck is going on. 

It looks like some fresh out of college Computer Science person decided to try to be clever and made everything #defines so you cannot look at the variables with the debugger. 

This is the stupidest thing I have ever seen. And I have been doing this for over 40 years, and have seen a lot of stupid things. 

Now what am I supposed to do? Rewrite it from the registers in the datasheet and screw these stupid structures?

Why would anyone think this was a good way to write code? You have made it impossible to debug.

Congratulations. You have won the The International Obfuscated C Code Contest. I will not be recommend this processor in our company for anything.  

In the meantime I still have to work with it on this stupid project. 

Kip



RM57L843: Recommended SDRAM

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Part Number:RM57L843

Do we have any recommended SDRAM part numbers to work with Hercules MCUs? It looks like the SDRAM previously used with these devices (IS42S16400F-7BL) is now obsolete.

TAS2552: I2C Slave NAK

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Part Number:TAS2552

Hi Team,

My customer is seeing intermittent problems on their I2C bus in which they are getting NAK from the TAS2552 slave intermittently. Initially we thought it was the audio chip NAKing our I2C master but looking at oscilloscope traces we noticed that something else could be going wrong. I'd like to get your help on what might be the cause of this problem.

Before I jump into the explanation, here is an outline of their setup:

1) Our Device which has an I2C master FSM and digital PDM CLK and DATA driver

2) The I2C signals (SCL/SDA) and the PDM signals (PDM/PDM_CL) from our device connected to pins on JP3 + GNDs

3) 5 V and 3.3 V to the EVM provided from a bench top supply

4) The differential analog audio output connected to a 8 ohm speaker

Our application programs the I2C registers in the audio chip to setup it up for PDM mode and once that is done, we start driving PDM clock and PDM data.

Sometimes when running the I2C initialization we intermittently get a NAK (as seen by our I2C master). The analysis at this point is that our I2C master FSM is getting confused sometimes because of the way SDA is released on the falling edge if SCL by TAS2552 during the ACK phase. Please see the attached scope captures of the 9th clock pulse (which is the ACK phase), one with our I2C master (TAS2552_ACK_Phase) and another with the I2C master that is on the EVM board (EVM_I2C_Master_TAS2552_ACK_Phase)

TAS2552_ACK_Phase:

EVM_I2C_Master_TAS2552_ACK_Phase:

As you can see in the first case, the SDA line is released while the SCL line is still falling. Sometimes this looks like SDA changing while SCL is high (looks like a repeated start condition which confuses our master). The result is unpredictable behavior after this point. If you notice in the second picture, there is some separation between the SCL falling and the 'glitch' where TAS2552 released the bus and the I2C master took over.

I understand that this a function of pull resistors/capacitance on the bus. One thing that we were curious about is that TAS2552 does not seem to be providing and HOLD after the falling edge of SCL (o hold). According to the TAS2552 datasheet a minimum HOLD of 10 ns is specified. Is this a requirement on the inputs only? What are the output HOLD values? Also, if you notice in the first picture, the TAS2552 is not able to drive the SDA line all the way to GND. We do have stronger pullups on this line (~1.5K) in parallel with the 10K on the EVM board which results in ~1.3K of effective pull resistance on each line. So the current sink requirements are 3.3V/1.3K (3.3 V is the IOVDD in our case) which is ~2.5 mA of current which is less than the 3 mA minimum requirement for I2C. This seems reasonable, but the observation is that TAS2552 is not able to sink that much current. 

Any guidance/information you can provide will be much appreciated.

Thanks,
Mitchell

TPS63070: FB voltage drop when switch power supply

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Part Number:TPS63070

Hi

I am using TPs63070  to get 4.7V output in UPS system. The problem is when the unit is powered by Battery(6V) I am getting 4.72V with FB of 0.813V which is fine but as soon as I connect the power supply (9v) the voltage drop to 4.59V and FB become 0.768V which is wrong. 

Can you tell me why  FB is dropping voltage when I change the power supply? 

Schematic : e2e.ti.com/.../730714

LMZ14202H: Regulator failure at 32VDC Input

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Part Number:LMZ14202H

Hello there,

I have been designing a product around the LMZ14202H regulator. Basically, we have a product we want to operate in the range of 12-36VDC. All is well until we get to about 32VDC at which point when power is applied to the regulator circuit (cold boot up/zero voltage state), it fails almost immediately and becomes a direct short on my power supply feeding this test circuit; after which point the regulator is toast and will no longer function. If I replace with a new regulator, everything works fine when I keep it below 32VDC.

Using the TI suggested component values as per the spec sheet for a 12VDC output, with the change of the CSS capacitor being 0.1uf now because I thought this issue was related to a high inrush current on the load. This issue existed prior to this change also, with the suggested value of 4200pF cap. Here are the component values:

RFBT:  34K

RFBB:  2.43K

RON:  249K

COUT:  47uF

CSS:  4700pF and also tried 0.1uF

Any ideas where to look that might be causing the issue? 

UCD90160A: Current monitoring not configurable in Fusion Digital Power Designer

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Part Number:UCD90160A

We are using a UCD90160A but are not able to configure MON pins for current monitoring, even though the pins are available.  The Temperature and Current columns in the Hardware configuration tab show up as "N/A. Sequencing, monitoring and programming all work properly.

When using the default configuration on the device supplied with the  eval board, current and temperature did appear to be configurable. Version number is V7.1.1

Thanks

Bernard Harris

TINA/Spice: Plotting Impedence vs Frequency in TINA

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Tool/software:TINA-TI or Spice Models

Here is my circuit. I am setting the current generator to sweep up to 100MEG using the Control Object parameter.

But how do I actually get TINA to plot this? I want to see what the voltage across the current generator/ divided by the current, over 0 - 100MHz.

 Seems like noone of of the analysis options are giving me what I want.

CC1352P: SW tool for mass production burning of CC1352P

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Part Number:CC1352P

Hello,

I'm working on a product using CC1352 PG2.1, and preparing production line environment. 

What is the TI recommendation for a tool to burn CC1352P PG2.1 in the production line?

Command line support is prefereable to enable automation, but other automation interfaces can be considered too (e.g. DLL).

Can FLASH-PROGRAMMER-2 be used for that purpose?

If there are several candidates, please list pros & cons. For example, will the tool be able to report statistics, retry on failures, etc'? 

Thanks,

Amit


CCS/TMS320F28379D: How can I write my code on the Flash?

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Part Number:TMS320F28379D

Tool/software: Code Composer Studio

Hello,

I have written a code in CCS and when I want to upload it to the RAM, it gives an error that the program does not fit into the available memory. So I want to load the program into the FLASH which has more space. In order to do that in C2000 Linker>file search path, I add the 2837xD_FLASH_Ink_cpu1.cmd file. However, after debugging the code when I click the run button, I get this message:

Break at address "0x3fe493" with no debug information available, or outside of program code.

How should I solve this issue? Is there any other way to load the program into the FLASH memory?

Regards,

Ata

ADS1263EVM-PDK: MMB0 REV D schematic

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Part Number:ADS1263EVM-PDK

Could you please where I can download the schematic of MMB0 board?

Thanks,

LH Ji

TPS65983: Creating Flash Image for Thunderbolt 3 Using TPS65983

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Part Number:TPS65983

Could someone please comment on the steps below for creating a flash image for the TPS65983 from a TI perspective?  Our design is not powering up properly and suspect the firmware was not built properly:

Thanks!

---John

Software Tools

Tool

Source

Version

Description

TPS65983 Application Customization 3_19

T.I.

3.19

This utility creates and modifies the TPS65983B power delivery portion of the firmware stored in flash.

Imaginarium2

Intel

4.11.8

This tool is the “Thunderbolt NVM customization tool”.

 

It “allows customization of Titan Ridge and Alpine Ridge Firmware for use in Thunderbolt products”.

 

Note that this tool does NOT interact with hardware, but only with image files. You open an existing image file and edit it. This tool can also merge in new T.I. PD firmware.

 

It is run as a portable application and doesn’t require installation.

TenLira

Intel

 

This tool is used to read and write to flash.

Flash_Tool

Intel

3.2.1

This command line tool programs flash.

 

TenLira Manufacturing Tool version 3.2.0 must be installed

 

 

 

 

 

 

Step 1: Run the TI TPS65983 Application Customization Tool

  • Run latest version of TPS65983 Application Customization Tool version (3.19 when this document was last updated)

 

  • Select “Change File” to select Firmware Base Image: “tps65982_v0006.49.00.bin”
  • Select Project / New Project / Which reference design are you using: “Bus-powered Device”
  • Is your system PD3 compliant? “Supports PD3 and PD2”
  • Does this device sink power on the internal HV path (3A max) or external (5A max)?: Internal
  • Select Binary / Save Binary
  • Check Full Flash Image, binary file format, and select a filename: TPS65983B_PD_full_image.bin
  • Region 1 offset: 0x2000 (default)
  • Region 2 offset: 0x15000 (default)
  • The binary file will then be created; Intel Imaginarium2 tool will merge with TB firmware

 

STEP 2: Use the Intel Imaginarium2 tool to prepare a firmware image for the TB3-TO-CMC-LP

  • Run latest version of Imaginarium2 (v4.11.8 when this document was last updated)

Page #1) Load Intel-provided firmware image: “LP_EP_2C_A1_rev15_NOSEC_sign.bin”

Page #2) Select Default Configuration “Alek Creek – BPD 1 port”

Page #4) Required Mbps: 100”

Page #4) Maximum Mbps: 10,000”

Page #4) Device Power – Select “Bus Power”

Page #4) Select active CIO lanes in bus-power mode: “2 lanes enabled”

Page #6) PCIe Lane Config: 1x2

Page #6) PCIe Deemphasis: -6 dB

Page #6: Subsystem Vendor ID: 0x8086

Page #6: Subsystem ID: 0x0000

Page #7: PCI Enablement (Device 0 and Device 1): all unchecked

Page #8) Change Vendor Name from “Intel” to “Abaco”

Page #8) Change Model Name from “Alek Creek” to “our_model_name

Page #8) Change Vendor ID from 0x8086 to 0xhhhh (our Intel vendor ID)

Page #8) Change Model ID from 0x0004 to 0xhhhh (our model ID)

Page #8) Change Model Revision to “1”

Page #8) Change NVM Revision to “1”

Page #13) Choose CIO lanes P/N swaps:

  • PA_CIO0_TX_PN (unchecked)
  • PA_CIO0_RX_PN (unchecked)
  • PA_CIO1_TX_PN (unchecked)
  • PA_CIO1_RX_PN (unchecked)

Page #14) Set all Tx Forward Feedback Equalizer fields to “1”

Page #16) Thunderbolt Port A Configuration: “Thunderbolt Multi-Function”

Page #23) USB2 amplitude: 0x88

Page #24) Set LTR into device: unchecked

Page #26) External GPU device?: unchecked

Page #27) USB 3.1 Presets: leave at default

Page #31) Leave all other fields unmodified.

Merge NVM with PD firmware? (Select “Yes”)

PD FW Rev: 0x0000

Page #32) Save image to file: TB3-TO-CMC-LP_rev2.bin

Save configuration to XML file? (you check this box and save configuration to file tb3-to-cmc-lp-rev1.xml)

 

Step 3: Program flash device (Winbond W25Q80DV) using ALL-100 programmer from Hi-Lo systems

This programmer can directly use the binary file image previously created.

 

Step 4: Solder flash device to PCB.

DS90UB954-Q1: Enabling self trigger for AR0233

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Part Number:DS90UB954-Q1

Hello,

First question======

We are using serial (MIPI) MARS camera (AR0233 -> TI953) and we are receiving at our board using TI954 and TI954 interface FPGA using MIPI.

So far, we are able to 

1. Enable pattern generation at TI954 and receive at FPGA

2. Access back channel I2C at TI954 and read from TI953.

So, interface between camera and TI954 looks OK and interface between TI954 and FPGA looks OK.

I think trigger has some issue at TI954. We connected trigger signal to TI954 GPIO0 and GPIO1. (2 cameras to TI954)

My question is how to enable self trigger at camera using I2C access to TI954 (back channel to camera) and receive frames at FPGA.

Could any of you can give me register sequence to try this ?

Second question======

If we use parallel MARS, we cannot access 913 serializer using TI954 back channel. I don't understand what is the difference and what I am missing.

Any suggestions ?

Thanks !

TINA/Spice/TPS7A90: Model conversion Spice to TINA

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Part Number:TPS7A90

Tool/software:TINA-TI or Spice Models

Dear all,

I was following the step by step procedure to convert a Spice model in to TINA-TI model.

I got a syntax error while compiling the transient model of the TPS7A9 ()

The error is related to the line 94: X_u3_U1_U7         u3_U1_EN11 u3_OK d_d PARAMS:

Can you help in the conversion process ?

regards,

Domenico

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